Fbb CMOS Tapered Buffer With Optimal Vth Selection
HARPREET KAUR* , AJAYPAL SINGH and LIPIKA GUPTA Department of Electronics and Communication, Chitkara University, Himachal Pradesh-125001, India *E-mail: harpreet.kaur@chitkarauniversity.edu.in Abstract: This paper represents fixed body biased CMOS Tapered Buffer which is designed to minimize the PDP (Power Delay Product) of the circuit. CMOS Tapered Buffers are often used for driving large capacitive load at high speed. Since there are tradeoffs between performance parameters of Buffer for minimizing its PDP value and due to technology constraints on the threshold voltage of MOS; one can vary the Vth up to certain limit while keeping the VDD constant. The proposed work is helpful in designing power efficient CMOS Tapered Buffer. This is found that in proposed Buffer when Vth value for the first stage of inverter is taken between the range of (0.2VDD - 0.4 VDD), its performance gets improved in terms of power dissipation. This analysis is verified by simulating the 2-stage Tap...